Many programmable digital devices, such as microprocessors, have a shared dual-access scratch-pad memory. For example, when two such microprocessors share a message buffer between them, each processor needs both a read and a write port.
Thus, so-called dual-access memories are commonly-employed in programmable digital devices. Presently, these memories are constructed from a number of separate integrated circuit chips which will typically include a pair of separate single-access memory chips with a multiplexer on a third chip connected to the input ports of the memories. Access to one or the other of the memories is controlled by a memory switching signal applied to the multiplexer.
The presence of an external multiplexer has a number of undesirable consequences: an overhead time penalty is added to all memory accesses and more complex timing control requirements are necessitated by the need to apply the memory switching signal sufficiently in advance of the access to allow stabilization of the signal paths passing through the multiplexer; in many instances a separate multiplexer switching clock was used.
Even if these undesirable consequences are considered manageable, a further difficulty with the use of two single-access memories and the inter-memory switching multiplexer is that this arrangement does not permit independent reading and writing, from both the input ports and the output ports, as may be needed in a particular application. Presently, another off-chip multiplexer is used to switch from read to write address. The use of an external read/write multiplexer entails further difficulties: additional timing signals were necessitated, usually supplied by a separate write clock which had a critical ten nanosecond timing window during which the address signal must stabilize in order to avoid race conditions. This was a major nuisance in the design of a working memory.
Further, since it is desirable to be able to access the data stored in any given location from either port, the data must be replicated in both single-access memories. In prior art memories of this construction, an additional clock phase is typically added to transfer data written into a given location in one of the singleaccess memories to the other single-access memory, thereby imposing a significant time overhead in the cycle time of the memory.
The use of a number of separate chips to form the dual-access memory increases the cost of fabrication due to the large number of terminal pins which must be interconnected and decreases the access speed, over and above that already mentioned, due to inter-chip signal propagation delay.
Additionally, present dual-access memories use bi-directional busses to connect the individual storage locations to a single set of terminals used for both input and output. This technique is slow in that it requires a reversal of the bi-directional busses for each access cycle.
Finally, present memories support byte-oriented operations through the use of separate memories, one for each byte. This method involves duplication of much of the peripheral elements supporting the memories resulting in more expensive device with a greater number of pin interconnections.
In another application, a four read-port, two write port memory is to be shared by a two-input arith- metic-logic (ALU) and a two-input multiplier processor. In this case, two read ports are connected to the input of the ALU and the remaining two read ports are connected to the inputs of the multiplier. The ALU output is connected to one of the memory write ports and the multiplier output to the other write port of the memory. Thus, it is desirable to be able to expand in a parallel manner a dual-access memory so that arithmetic addition and subtraction by the ALU can be performed in parallels with multiplication and division by the multiplier.